The invention relates to a dynamic amplifier circuit for amplifying a signal in a first time interval, under control of a clock signal, which circuit comprises a bias circuit for obtaining a bias current in the amplifier circuit during said first time interval, which bias current decreases from an initial value. Such dynamic amplifier circuits are inter alia used in switched capacitor filter circuits in order to obtain the filter action and have been proposed in order to replace operational amplifiers in such circuits in inter alia:
Copeland, M. A. and Rabaey, J. M.: "Dynamic amplifier for M.O.S. technology", Electronics Letters, 1979, Vol. 15, No. 10, pages 301-302,
Hosticka, B. J.: "Dynamic amplifiers in C.M.O.S. technology", Electronics Letters, 1979, Vol. 15, No. 25, pages 819-820, and
Hosticka, B. J.: "Dynamic C.M.O.S. amplifiers" I.E.E.E. Journal of Solid-State Circuits, Vol. SC-15, No. 5, pages 887-894; which publications are herewith incorporated by reference.
The advantage of such a dynamic amplifier circuit is that at the beginning of the amplifying period, i.e. said first time interval, the bias current of the amplifier circuit is large, which means a high amplifier circuit speed at the beginning of the amplifying period, and that at the end of the amplifying period the bias current is small, which means a high gain and hence a high accuracy at the end of the amplifying period.
A switched-capacitance arrangement comprising such dynamic-amplifier circuits is found to be highly susceptible to interference, in particular at the end of the first time interval, when the bias current may be very small, and during a subsequent time interval in which the amplifier is turned off. Moreover, it has been found that such amplifier circuits present problems when a capacitance, for example the input capacitance of a following stage, is arranged between the outputs of two such dynamic amplifier circuits.